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Silicon nanowires nanoscale electronic devices

wallpapers News 2020-05-28
The circuit of the single electron detector contains multiple tunnel junctions (MTJ), which transfer electrons to and from the storage node, and the connected single electron tunneling transistor (SETTs) can simultaneously and accurately calculate the electrons moving to and from the storage node.

Using phosphorus doped silicon nanowire studied the single electron probe, specific preparation process is: first use phosphorus doped silicon nanowires with two single electron transistors, including nanowires phosphorus of the doping elements to form the conductive island and MTJ, then use photolithography and EB technology will contain the mutual connection and the bonding area of circuit focused on SOI wafer, chip consists of three parts: in the middle of phosphorus doping concentration of 1 x 1019 cm - 3, 40 nm silicon nanowires layer thickness, the bottom for the silicon substrate, separated with 350 nm thick oxide layer, the top for SiO2 protective layer. After metal gasification and splash into the film, SOI wafer with RIE technique be moved to the silicon substrate, to reduce the number of nanowires cross knot, reoccupy oxide passivation for this device, single electron storage element using doped silicon nanowire coulomb jam effect can realize the preparation of single electron storage element, has been with several single electron storage components, electronic point near pathway of transistor voltage changed after storage nodes. Stone et al. prepared a single-electron storage element containing heavy phosphorous doped silicon nanowires using a process similar to that of CMOS.

 

Due to the uneven distribution of materials in the device among the conductive islands, a large number of tunnel barriers were formed, so this device has a good coulomb blocking performance when the temperature is greater than 4.2k. The specific preparation process is as follows: MTJs silicon nanowire was prepared with a diameter of about 50 nm and a length of 500 nm. The top of the SOI chip is a 40nm thick silicon layer, the bottom is a silicon substrate, the middle is separated by a 350 nm thick oxide layer, and the top is a 20 nm thick oxide protective layer. The silicon layer injected to a depth of 40nm has a phosphorus doped concentration of 1×1019 cm-3. Using EB and RIE technique in SOI substrate with integrated circuit chips, and on the chip with 200 nm thick photoresist layer, electron beam diameter less than 10 nm high-resolution electron beam lithography system is used to limit the circuit on the photoresist, RIE circuit used to be moved to the SOI wafers, then connect the circuit by EB process electronic contact element. In order to enhance the insulation performance and prevent the size of nanowires from being smaller than the etching size, the surface oxide layer was removed after the chip was oxidized at 1 000℃ for 15min in a dry oxidation atmosphere, and the aluminum was gasified to form a 400 nm thick aluminum layer so that the chip had good ohmic contact performance.The circuit of the single electron detector contains multiple tunnel junctions (MTJ), which transfer electrons to and from the storage node, and the connected single electron tunneling transistor (SETTs) can simultaneously and accurately calculate the electrons moving to and from the storage node.

Silicon nanoparticles are crystalline silicon particles less than 5 nanometres (1 billion billionths of a metre) in diameter. 

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Tag: Silicon nano